library verilog;
use verilog.vl_types.all;
entity dbg_crc8_d1 is
    generic(
        Tp              : integer := 1
    );
    port(
        Data            : in     vl_logic;
        EnableCrc       : in     vl_logic;
        Reset           : in     vl_logic;
        SyncResetCrc    : in     vl_logic;
        CrcOut          : out    vl_logic_vector(7 downto 0);
        Clk             : in     vl_logic
    );
end dbg_crc8_d1;
